1. Field of the Invention
The present invention relates to a method and a device for performing switching and data comparison in a computer system having at least two processing units.
2. Description of Related Art
A method for detecting errors in a comparative mode is described in published international patent document WO 01/46806. In this context, the data are processed in parallel in a processing unit having two processing unit ALU's and are compared. In this published document, if there is an error (soft error, transient error), both ALU's work independently of each other until the erroneous data have been removed, and a renewed (partially repeated) redundant processing can be undertaken. This assumes that both ALU's work synchronously with each other, and that the results can be compared in a clock accurate manner.
Methods are known in the related art as to how one may switch over between a comparative mode for error detection, in which tasks are executed redundantly, and a performance mode for achieving greater working capacity. The condition is that the processing units for the comparative mode are synchronized with respect to each other. For this, it is required that the two processing units are able to be stopped and that they work synchronously with clock accuracy, in order to be able to compare to one another the resulting data as they are written into the memory. This calls for interventions in the hardware, and individual design approaches are proposed.
In published European Patent EP 0969373, by contrast, a comparison of the results of redundantly working processing units or processing units are assured even when they work asynchronously with respect to each other, that is, not with clock accuracy, or having an unknown clock pulse offset.
Voting systems are known from the aircraft industry which are able to use inputs from standard computers, and are able to process these safely by a voter-basis decision, and thereby are able to trigger safety-relevant actions. One system which combines inter-processing unit and inter-control unit communications with each other is the FME system, in which, because of a high degree of redundancy, the system remains operational even in the case of individual or even a plurality of errors, and which was developed by DASA for space flight—see, e.g., (Urban, et al.): “A survivable avionics system for space applications,” Int. Symposium on Fault-tolerant Computing, FTCS-28 (1998), pp. 372-381). This system can even tolerate byzantine errors (that is, especially nasty errors in a case where not all components receive the same information, but a schemer even “deliberately” distributes different wrong information to various components). Such a system is commercially applicable, because of its high cost, for particularly critical systems which are manufactured in very small numbers. A cost-effective design approach is not known that can be produced in large numbers and additionally has switchover facilities. Therefore there exists the object of creating a switchover and compare unit which permits switching over the operating mode of two or more processing units, and, in this context, is able to do without interventions in the structure of these processing units and also requires no additional signals for this purpose. In this context, it is supposed to be possible to compare to one another various digital or analog signals from various processing units in a comparative mode. In this context, under certain circumstances, this comparison should even be possible if the processing units are operated using different clock pulse signals, and not synchronously with respect to one another. Beyond that, it is the object of the present invention to make available means and methods by which the comparison is also able to be carried out using various clock pulses.